Vlsi Technology LLC v. Intel Corporation

Citation: Not availableDocket: 21-1826

Court: Court of Appeals for the Federal Circuit; November 14, 2022; Federal Appellate Court

Original Court Document: View Document

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Intel Corporation initiated three inter partes review (IPR) petitions against VLSI Technology LLC's U.S. Patent No. 7,247,552, claiming the patent's challenged claims were unpatentable. The Patent Trial and Appeal Board (PTAB) agreed and issued a combined Final Written Decision confirming this unpatentability. The patent concerns a method to mitigate damage to bond pads of integrated circuits (ICs) when forces are applied during attachment to other components. The '552 patent describes an IC structure that includes metal interconnect layers and bond pads, with the latter being susceptible to damage due to external forces. It posits that dedicated metal support structures can enhance durability while allowing interconnect layers to remain functionally independent for other circuit uses. The patent further specifies that only a minimum density of metal is necessary for adequate support, with the option to add 'dummy metal lines' if the existing density is insufficient. The court affirmed in part, reversed in part, and remanded the case for further proceedings.

Claim 1 of the '552 patent is the sole independent apparatus claim and represents the patented invention. It describes an integrated circuit with specific components: a substrate containing active circuitry, a bond pad situated above the substrate, a susceptible force region beneath the bond pad, a stack of interconnect layers (each with a portion in the force region), and interlayer dielectrics that separate these layers, including at least one via for interconnection. Notably, at least one interconnect layer features a functional metal line beneath the bond pad, which is not electrically connected to it, serving instead for wiring to the active circuitry. Additionally, dummy metal lines are included in the force region to maintain a predetermined metal density.

Claim 2 is dependent on Claim 1, while Claim 11 is a method claim related to Claim 1. Claim 20 outlines a method for fabricating an integrated circuit with multiple bond pads, detailing steps from circuit design to layout modification by adding dummy metal lines to achieve a specified metal density.

In 2018, VLSI sued Intel for infringing the '552 patent in the District Court of Delaware, where a claim construction hearing was held. The court defined 'force region' as an area where forces act on the interconnect structure during die attach. In June 2019, prior to claim construction, Intel petitioned for inter partes review (IPR) to contest the validity of claims 1, 2, 11, and 20, proposing a construction for 'force region' that aligned with the court's definition. Despite seeming agreement on the term 'force region,' a disagreement surfaced regarding 'die attach.' Intel interpreted 'die attach' broadly, including methods like wire bonding, which VLSI did not contest before the Board.

VLSI contended that "die attach" specifically refers to "flip chip" bonding, excluding wire bonding. This interpretation was central to its distinction of Intel's primary prior art reference, U.S. Patent Publication No. 2004/0150112 (Oda), which involves wire bonding. VLSI asserted that since Oda did not demonstrate a "force region" as defined by the '552 patent claims, it did not invalidate those claims. The Board, however, disagreed with VLSI’s restrictive definition, noting that Intel provided evidence that wire bonding qualifies as a type of die attach, thus supporting the existence of a "force region" in Oda. The Board emphasized that VLSI's own proposed construction acknowledged regions under the bond pad, aligning with the plain language of the claims. In its Final Written Decision, the Board ultimately did not resolve the dispute over "die attach" but defined "force region" as including at least the area directly beneath the bond pad. Furthermore, the Board clarified that the '552 patent specification indicated "force region" was not limited to flip chip bonding and could encompass wire bonding, leading to the conclusion that Oda disclosed the "force region," rendering claims 1, 2, and 11 unpatentable for obviousness. Regarding claim 20, VLSI argued that "metal-containing interconnect layers" required a connection to active circuitry, while Intel contended that the claim did not necessitate such a specification. The Board agreed with Intel, stating that claim 20 does not mention "active circuitry" and interpreted the phrase to include interconnect layers that are electrically connected to each other but not to the bond pad.

Intel primarily relied on U.S. Patent No. 7,102,223 (Kanaoka) to support the 'used for electrical interconnection' limitation in claim 20, as interpreted by the Board. Kanaoka's Figure 45 illustrates a die with interconnect layers linked by vertical metal 'vias.' The Board determined that since these layers were electrically connected but not to the bond pad, they satisfied the 'used for electrical interconnection' requirement. Consequently, the Board ruled all challenged claims of the '552 patent (claims 1, 2, 11, and 20) were unpatentable, prompting VLSI to appeal.

On appeal, VLSI raised two main issues: first, a claim that the Board mishandled the 'force region' limitation in claims 1, 2, and 11; second, a challenge to the Board's interpretation of 'used for electrical interconnection' in claim 20, arguing it shouldn't include metallic structures not connected to active circuitry. The court affirmed the Board's decision regarding the first issue but reversed and remanded on the second.

Regarding the 'force region' limitation, VLSI contended that the Board failed to properly consider the district court's claim construction. VLSI cited regulations requiring the Board to give due weight to prior claim constructions. However, the court rejected this argument, noting that the Board was aware of the district court's construction, which had been extensively discussed during the proceedings. The Board did not dismiss the district court's definition but recognized a deeper dispute surrounding whether 'force region' pertained only to flip chip bonding or also included wire bonding. The district court had not definitively ruled on whether 'die attach' encompassed wire bonding, allowing the Board to address issues not raised at the district court level without conflicting with its prior conclusions.

The Board's treatment of the term 'force region' is upheld as not erroneous. The dispute required the Board to extend beyond the district court's claim construction, making reference to it unnecessary; thus, any omission was a harmless error. The Board's construction of 'force region' aligns with the specification in the '552 patent, particularly a passage in column 3 that details how forces are exerted on the interconnect structure during die attachment. Although the term 'die attach' might be interpreted to include only flip chip bonding, this does not limit 'force region' since claims shouldn't be confined to specific embodiments. The specification also explicitly references wire bonding and states that the invention is not restricted to flip chip bonding. Additional passages indicate that the 'force region' encompasses broader contexts of stress susceptibility from bond pads, not limited to flip chip bonding processes. The Board correctly concluded that the Oda reference meets the 'force region' requirement, with the proper construction defined in column 6 as a region where interconnect layers are susceptible to stress from the bond pad due to assembly or other processes.

Stresses on interconnect layers from assembly processes, including wire bonding, are encompassed by the term 'force region' as interpreted by the Board. The Board’s definition aligns with the '552 patent’s language, confirming that the Oda reference illustrates the 'force region' of claim 1. The Board established that the 'force region' includes at least the area directly beneath the bond pad, without restricting it solely to flip chip bonding scenarios. Consequently, claims 1, 2, and 11 were deemed unpatentable based on the Oda reference and others.

VLSI challenges this interpretation on two fronts. First, it argues that defining 'force region' as being at least under the bond pad is flawed because it reiterates claim requirements, potentially rendering them redundant. Although constructions introducing redundancy are typically avoided, they are not prohibited, particularly when intrinsic evidence supports the construction’s validity. The claim’s language indicates that the 'force region' is defined as being directly under the bond pad, which is clear despite its potentially awkward phrasing.

Second, VLSI contends that the Board is obligated to adhere to any agreed-upon claim construction during an IPR, regardless of its correctness. VLSI cites precedent from SAS Institute v. Iancu and other cases to support this view. However, the Board disagrees with this interpretation, affirming that the petition guides the IPR process and that the Board must base its decisions on presented arguments, allowing for appropriate responses from opposing parties.

The petition delineates the scope of the Inter Partes Review (IPR) proceeding, with the Board required to base its decisions on arguments presented by the parties, allowing for responses from opposing parties. While the Board may adopt its own claim constructions, it is not restricted solely to those provided by the parties. In the case at hand, although Intel's proposed construction of 'force region' was not opposed by VLSI, a significant disagreement regarding the term 'die attach' existed, justifying the Board's independent claim construction. Consequently, the Board's analysis regarding the 'force region' limitation was affirmed as correct. 

VLSI contends that the Board's construction of the phrase 'used for electrical interconnection not directly connected to the bond pad' in claim 20 of the '552 patent was overly broad. The Board interpreted this phrase to include interconnect layers that are electrically connected to each other but not to the bond pad or other active circuitry. VLSI argues that its interpretation necessitates a connection to active circuitry or the capacity to carry electricity, which the Kanaoka reference fails to disclose. The summary indicates agreement with VLSI's view that the Board's interpretation was too expansive, noting that the claim’s wording suggests actual use of the interconnect layers for electricity conveyance, and that the mention of 'dummy metal lines' signifies that the claimed interconnect layers should be capable of carrying electricity.

The file history of the '552 patent reveals that the phrase "used for electrical interconnection not directly connected to the bond pad" was added to claim 20 during prosecution. This claim describes a method for making an integrated circuit with multiple bond pads and specifies that certain metal interconnect layers extend under a bond pad without being electrically connected to it, as they are utilized for electrical interconnections not directly linked to the bond pad. The Board noted that this amendment seemed to clarify what the interconnect layers could not be connected to, rather than what they must connect to. However, this interpretation fails to explain the significance of the added phrase, which should have independent meaning. The applicant previously contended that areas under bond pads could not be used for unrelated wiring, suggesting that the added phrase indicates that interconnect layers must conduct electricity to components other than the bond pad. Intel's argument that interconnect layers can be "electrically connected" without carrying electricity is flawed because the claim specifies "being used for electrical interconnection," implying functionality. Consequently, VLSI's interpretation, which requires interconnect layers to be capable of carrying electricity or connected to active circuitry, is accepted. The Board's construction of this phrase is reversed, and the patentability of claim 20 is remanded to the Board for reconsideration of Intel's obviousness arguments. The Board's handling of the term "force region" is affirmed, and claims 1, 2, and 11 are deemed unpatentable. The final decision is partially affirmed, partially reversed, and remanded.