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Silicon Graphics, Inc. v. N Vidia Corp.
Citations: 58 F. Supp. 2d 331; 1999 U.S. Dist. LEXIS 9693; 1999 WL 428234Docket: Civil Action No. 98-188-RRM
Court: District Court, D. Delaware; June 24, 1999; Federal District Court
Silicon Graphics, Inc. filed a patent infringement lawsuit against NVIDIA Corporation, claiming willful infringement of U.S. Patent No. 5,706,481, which pertains to a method for texture mapping and a semiconductor chip designed for the same. Silicon Graphics asserts that NVIDIA's graphics processor chips, including RIVA 128 and TNT series, infringe on specific claims of the patent. NVIDIA has counterclaimed, seeking a declaratory judgment of the patent's invalidity and non-infringement. The case is set for jury trial on July 12, 1999. The court previously held a Markman hearing to construe disputed patent terms. Both parties provided evidence, including expert declarations and the patent's file history, for the court's consideration. Silicon Graphics is based in Mountain View, California, while NVIDIA operates out of Sunnyvale, California. The patent was issued on August 20, 1997, to inventors Marc R. Hannah and Michael B. Nagy, who assigned it to Silicon Graphics. The technology at issue involves the representation of three-dimensional objects on two-dimensional displays, with applications ranging from video games to film special effects. Objects in computer graphics are defined by vertices with x, y, and z coordinates, forming polygons when connected, with triangles being the simplest. Three-dimensional shapes arise from connecting multiple two-dimensional polygons, while curved surfaces are approximated by small polygons. A wire frame view displays the outlines of these 3-D shapes. Texture mapping enhances the realism of rendered 3-D objects by applying surface textures to wire frame models, described by Silicon Graphics as the process of overlaying a two-dimensional texture on a three-dimensional object to provide detail and spatial cues. A texture map consists of "texels" or texture elements, representing the surface pattern, akin to wrapping a design around a geometric form. An example of this is mapping a wood grain texture onto a cube. Texture data is typically retrieved from storage and loaded into the computer's main memory, then sent to an interpolator, which converts this data into pixels, the smallest color units on a screen. This process may include additional effects like lighting and fogging. The '481 patent, titled "Apparatus and Method for Integrating Texture Memory and Interpolation Logic in a Computer System," addresses inefficiencies in previous texture mapping systems, particularly the excessive resource consumption and bandwidth limitations caused by transferring texture data between semiconductor chips. The patent highlights that this data transfer burdens the texture mapping process, slowing down the exchange of critical information. Silicon Graphics outlines issues with texture mapping systems prior to the '481 patent, emphasizing that interpolators required texture data from main memory via a data bus, creating inefficiencies due to the slower data transport compared to the interpolator's processing speed. This resulted in delays and limited the operation of other components on the bus. The '481 patent addresses these inefficiencies by integrating a cache memory, termed TRAM (texture random access memory), on the same semiconductor chip as the interpolator. This setup allows the cache to store texture data, enabling quicker access for the interpolator and improving the speed and efficiency of texture mapping operations through a concept known as "locality of reference." The cache can preemptively store texture data, reducing reliance on the data bus and enhancing processing rates, thus conserving computer resources. The patent includes 18 claims, with Claims 1 and 10 being independent. Claim 1 is an apparatus claim describing the TRAM chip with four components: an input, a cache memory, an interpolator, and an output. Claim 10 is a method claim detailing the texture mapping process with three elements: storing texture data in cache, interpolating it to produce a pixel, and outputting that pixel. The dispute centers on whether the claims specify a cache memory that can store a complete texture mapping. Silicon Graphics accuses NVIDIA of infringing Claims 1-4 and 10-13 through its production of graphics processor chips such as RIVA 128 and TNT2. NVIDIA denies infringement and counters with claims challenging the validity of the patent based on indefiniteness, lack of enablement, anticipation, obviousness, and inadequate written description. NVIDIA has filed for summary judgment asserting it does not infringe the '481 patent, arguing that the term "texture mapping data" in Claims 1 and 10 necessitates on-chip storage of a complete texture pattern, which its chips do not provide. Additionally, NVIDIA claims that the fourth element of Claim 1 requires an output coupled to the interpolator, which its RIVA chips do not meet. In contrast, Silicon Graphics seeks summary judgment for literal infringement, contending that the court should reject NVIDIA's interpretations that impose limitations on the claims, specifically regarding the definitions of "complete" texture maps and "coupled" as meaning "directly connected." Silicon Graphics argues that with these limitations removed, NVIDIA's chips infringe Claims 1-4 and 10-13. NVIDIA also challenges the validity of Claims 1 and 10, asserting they are anticipated, obvious, lack adequate written description, and are indefinite, arguing against Silicon Graphics’ interpretation that the interpolator must be "dedicated" or a "specific device." The parties are engaged in a dispute over the meanings of several terms from the claims, including "cache memory," "output rendered pixel," "coupled," and "interpolator." Silicon Graphics advocates for the plain meaning of "cache memory," while NVIDIA argues it should imply a configuration for storing a complete texture mapping, based on the prosecution history of the '481 patent and its parent application. The prosecution history indicates that the '481 patent's predecessor, U.S. Patent No. 5,548,709, faced rejections from the PTO for claims being anticipated or obvious, particularly in light of a 1989 article on Intel's 80860 chip. The examiner noted the article described relevant technology that included memory management, data and instruction caches, and graphics circuitry for texture mapping. In response to the rejection, the applicants differentiated their claims from those described in the article. The applicants argued against the rejection of Claims 1, 10, and 19 by emphasizing that the Intel 80860 microprocessor, as described by Williams, lacks a dedicated memory unit for storing texture patterns, which is a critical feature of the present invention’s on-chip TRAM. They highlighted that while the 80860 can perform texture mapping, it requires off-chip memory access for texture patterns, unlike the present invention that allows direct storage on-chip, leading to superior performance with fewer off-chip accesses. The examiner acknowledged this in allowing Claims 1-18, stating that the prior art did not disclose several structural combinations unique to the present invention, including the dedicated memory unit and various processing capabilities. However, Claim 19 was rejected as it was deemed anticipated by the 80860 reference, which includes features relevant to the claim. Subsequently, the applicants canceled Claim 19, and the PTO allowed Claims 1-18, resulting in the issuance of U.S. Patent No. 5,548,709, assigned to Silicon Graphics. This patent describes a semiconductor chip for texture mapping, which includes a main memory, cache memory, interpolator, and a memory controller, distinguishing it from the earlier '481 patent that lacks on-chip memory controller or main memory. Claims 1 and 10 are identified as independent claims, with Claim 1 detailing the architecture of the semiconductor chip (TRAM) comprising six specific components necessary for operation. Claim 1 describes a semiconductor chip designed for texture mapping within a computer system, featuring several components: an input for textures, main memory for texture storage, cache memory for recently used textures, a memory controller to manage data transfers, and an interpolator to generate output rendered pixels based on textures from the cache. All these components reside on a single substrate. Claim 10 outlines a method for performing texture mapping using a semiconductor chip, consisting of six steps: inputting textures, storing them in main memory, caching recently used textures, controlling data transfers, using an interpolator to produce an output rendered pixel, and outputting that pixel from the chip. The prosecution history of the '481 Patent indicates that on May 22, 1996, applicants Hannah and Nagy filed Application No. 08/206,117 as a continuation of a prior application. Initially, it contained the original claims but later amendments cancelled these claims and introduced new ones (Claims 20-37), linked to Claim 19 of the prior application. These claims include a semiconductor chip with a cache memory and an interpolator, but lack the on-chip main memory present in the claims of the '709 patent. During prosecution, it was noted that the invention focuses on a dedicated graphics processing chip for texture mapping, emphasizing the unique combination of cache memory and interpolator on the chip. Previous claims were rejected due to prior art (Williams 80860 reference), which described a microprocessor with on-chip graphics that lacked the specialized architecture claimed by the applicants, particularly the capability of the cache memory to store a complete texture mapping, which is a key advantage of the present invention. The applicants assert that their invention, which features a semiconductor chip designed for graphics processing with a cache memory capable of storing a complete texture mapping, is not disclosed in any prior art references, and therefore should be allowed. The examiner, in a January 14, 1997 office action, rejected Claims 20-37 based on obviousness-type double patenting and identified Claims 20-28 as indefinite under 35 U.S.C. 112, second paragraph. The examiner compared Claims 1 and 2 of the '709 patent with pending Claims 20 and 21 of the '117 application, noting that the primary distinctions included the presence of an input for textures, the type of data stored in the cache memory, and the location of the main memory. The examiner suggested that it would have been obvious to one skilled in the art to substitute "a recently used texture" for "a complete texture mapping" in the cache. Similar comparisons were made between pending Claim 29 and Claims 10 and 11 of the '709 patent, with the same conclusion regarding obviousness. On April 29, 1997, the applicants amended Claims 20 and 29 to replace "complete texture mapping" with "texture mapping data" and added a requirement for an input configured to input texture mappings. The applicants submitted a Terminal Disclaimer to address the obviousness-type double patenting rejection and stated that their amendments responded to the examiner’s concerns under 35 U.S.C. 112. On April 30, 1997, they filed a Terminal Disclaimer agreeing that any patent from the '117 application would be enforceable only for the duration of the '709 patent. On August 20, 1997, the PTO issued a notice of allowability for Claims 20-37 of the '117 application, which became Claims 1-18 of the '481 patent, assigned to Silicon Graphics. The current disputes involve the interpretation of terms in the independent claims of the '481 patent, specifically Claims 1 and 10, which are equivalent to Claims 20 and 29 of the '117 application. Claim 1 describes a computer system with a semiconductor chip for texture mapping, detailing components such as an input for texture mappings, a cache memory for storing texture mapping data, an interpolator for generating rendered pixels, and an output for these pixels, all residing on a single substrate. Claim 10 outlines a method for texture mapping, including steps for storing texture mapping data in a cache memory on a semiconductor chip, producing rendered pixels via an interpolator, and outputting these pixels from the chip. The court is responsible for claim construction, guided by the legal standard established in Markman v. Westview Instruments, which mandates that claims be interpreted based on their ordinary meaning as understood by a person skilled in the art at the time of invention. The intrinsic evidence, including the claim language, specification, and prosecution history, is prioritized in this process, while extrinsic evidence may supplement understanding if necessary. The critical point of contention between NVIDIA and Silicon Graphics revolves around whether the phrases "a cache memory configured to store texture mapping data" in Claim 1 and "storing texture mapping data on a cache memory" in Claim 10 imply that the cache memory must hold a complete texture map, with NVIDIA asserting that it does and Silicon Graphics arguing that it does not. Silicon Graphics argues that the claims of the '709 and '481 patents do not necessitate a cache memory that stores a complete texture map but only requires storage for "data" related to "texture mapping." In response, NVIDIA asserts that the applicants effectively defined "cache memory" to mean one configured for complete texture mapping during patent prosecution. NVIDIA's claims rest on three arguments: first, that the applicants acted as their own lexicographers; second, that they disclaimed any definition of cache memory that does not involve a complete texture pattern; and third, that interpreting cache memory to store less than a complete mapping would render the claims obvious in light of prior art, specifically the Williams 80860 reference. The court recognizes that the plain language of Claims 1 and 10 does not explicitly call for a cache memory that stores a complete texture mapping. Instead, the terms used imply that the cache could store some texture mapping data. The court must determine if the applicants intended a meaning beyond the ordinary interpretation of these terms. Notably, the applicants previously described their invention as including an on-chip TRAM capable of storing a complete texture pattern and subsequently amended the claims to replace "complete texture mapping" with "texture mapping data," stating that the amendments aimed to more accurately reflect their invention's operations. Silicon Graphics argues that their current interpretation of cache memory is inconsistent with prior statements regarding the invention's architecture. The court must decide whether this inconsistency can be reconciled in the context of claim construction. It emphasizes that common terms should generally be interpreted by their ordinary meanings unless contextual evidence suggests otherwise. Silicon Graphics urges the court to view any discrepancies related to the Williams reference as an issue of obviousness. The court views the matter as potentially resolvable through claim construction, emphasizing the significance of prosecution history as intrinsic evidence in interpreting patent claims. In the prosecution history of the '709 patent, applicants distinguished Claims 1, 10, and 19 from the Williams 80860 reference by asserting that a key feature of their invention is the "on-chip TRAM" designed to store a complete texture pattern. Claim 19 specifically describes a TRAM with cache memory for texture information. The applicants implied that this cache memory must be capable of storing a complete texture pattern. Following the cancellation of Claim 19, they later refiled as the '117 application, where Claims 20 and 29 were based on Claim 19 and similarly claimed a TRAM with cache memory and interpolator, explicitly excluding on-chip main memory. When presenting these claims, the applicants reiterated the structural limitation requiring a cache memory configured for complete texture mapping. However, the examiner rejected Claims 1 and 10 on the grounds of double patenting, referencing "complete texture mapping" as a distinguishing element while subsequently deeming it obvious to substitute this with "a recently used texture." This reasoning appeared to misrepresent the patent chronology. The applicants resolved the double patenting issue by filing a terminal disclaimer, ensuring that any patent from the '117 application would share the same protection term as the '709 patent. Additionally, they amended Claims 20 and 29 to replace "complete texture mapping" with "texture mapping data." Silicon Graphics contends that this amendment indicates the applicants disclaimed the "complete texture mapping" limitation, which could represent a substantial shift in their claim if they had not already defined "cache memory" to store a complete texture mapping or aligned the meanings of the two phrases. Such a change would be significant, as it would omit a previously emphasized feature of their invention and attempt to reclaim a structure they had disclaimed. The court notes that if the applicants intended these significant alterations, they would have explicitly communicated this intention to the examiner, which they did not do. Applicants amended their claims to provide a more accurate representation of their invention, which they asserted should not alter the core description or structural limitations originally claimed. Specifically, they previously defined their invention as having a cache memory designed to store a complete texture mapping, a key characteristic that differentiates it from prior art. The amendments were intended to refine rather than contradict this definition, suggesting that the inclusion of the term "texture mapping data" was meant to enhance precision while preserving the structural element of complete texture mapping storage. Throughout the prosecution history, the applicants acted as their own lexicographers, clearly defining "cache memory" in a manner distinct from its ordinary meaning. For instance, in the '959 application, they indicated that the cache memory in pending Claim 19 was intended to store a complete texture pattern, even when that specific phrase was not included in the claim. This consistent application of their definition was maintained in subsequent applications, asserting that claims in the '117 application were also configured to store complete mapping data. Even after removing the words "complete mapping data" from some claims, the applicants argued that the intent behind the amendments was clarity rather than a change in the fundamental claim structure. The court recognizes that the applicants provided an explicit definition of "cache memory" and intended the phrase "texture mapping" to align with "complete texture mapping," reinforcing the requirement for cache memory to store a complete texture map. The public was entitled to rely on these representations made during the prosecution history, as established in relevant case law. In Digital Biometrics, Inc. v. Identix, Inc., the Federal Circuit determined that the public can rely on definitive statements made during patent prosecution for clarity in patent claims. The court interpreted "cache memory" in Claims 1 and 10 of the '481 patent as specifically configured to store a complete texture mapping. The court noted that it need not consider whether the applicants disclaimed chips storing less than a complete texture pattern because they had defined "cache memory" in a specific manner. Regarding the term "coupled" in Claim 1 of the '481 patent, Silicon Graphics argued it should mean any electrical connection, direct or indirect, while Vidia contended it should mean "directly coupled." The court highlighted that neither the claim nor the specification provided a definition for "coupled," leading both parties to reference dictionary definitions to support their positions. The court emphasized that claim terms are generally given their ordinary meaning unless explicitly defined otherwise by the patentee. The specification indicated that the cache is coupled to the input, suggesting that the term does not exclusively imply a direct connection. Figure 2 illustrates a TRAM embodying the inventions claimed in the '709 patent, where a DRAM array and input buffer are positioned between the cache and input line, indicating that "coupled" includes both direct and indirect connections. The specification and claims support this interpretation, particularly Claim 1, which describes an "interpolator coupled to said main memory and said cache memory." Notably, Figure 2 parallels Figure 2 of the '481 patent, showing the interpolator directly connected to the cache, but not to the main memory. The Federal Circuit allows for consideration of the prosecution history of a parent application in claim interpretation, as exemplified by Abtox, Inc. v. Exitron Corp. It is emphasized that an inventor typically does not define an invention in a manner that excludes a preferred embodiment, as noted in Hoechst Celanese Corp. v. BP Chemicals, Ltd. The document also addresses the proper construction of the phrases "an output coupled to said interpolator for outputting said output rendered pixel" in Claim 1 and "outputting said output rendered pixel from said semiconductor chip" in Claim 10 of the '481 patent. There is a dispute between n Vidia and Silicon Graphics regarding the meanings of "output," "outputting," and "output rendered pixel." n Vidia asserts that the '481 patent does not extend to further processing of the pixel after texture mapping by the interpolator, arguing that "outputting" from the interpolator is synonymous with "outputting" from the semiconductor chip. In contrast, Silicon Graphics maintains that these phrases should be understood in their ordinary sense, suggesting that the output and outputting described in Claim 1 pertain specifically to the interpolator, while Claim 10 pertains to the semiconductor. Silicon Graphics further argues that the claims allow for additional on-chip processing beyond texture mapping, which is pivotal in assessing the literal infringement dispute involving n Vidia's graphics chips, which perform additional processing like lighting and fogging effects before outputting pixels from the chip. n Vidia contends that a chip performing on-chip processing of a pixel after the pixel is output by the interpolator does not literally infringe Claims 1 or 10 of the '481 patent. The interpretation of "an output coupled to said interpolator for outputting said output rendered pixel" in Claim 1 suggests that the output from the interpolator does not have to be identical to the output from the semiconductor chip. The term "output rendered pixel" is not restricted to a pixel solely processed by the interpolator. n Vidia asserts that the inventors believed the outputs from the interpolator and the semiconductor were the same and that an "output rendered pixel" referred to a texture-mapped pixel without further processing before being output by both components. During the prosecution of the '709 patent, the applicants replaced "texel" with "output rendered pixel," clarifying that a texel refers to a pixel element with a texture mapped, available at the chip's output as a rendered pixel. However, this does not imply that the inventors thought the patent restricted mapping additional data onto the pixel after it was output from the interpolator but before it was output from the semiconductor. n Vidia argues that the patent specification indicates the "output rendered pixel" undergoes extra processing only after being output from the TRAM. They cite the specification stating that pixel data is sent to the raster subsystem for additional functions like z-buffering and blending. However, the Federal Circuit has established that specific embodiments in a patent should not limit the broader claim language. Thus, the court concludes that the cited specification does not exclude additional processing on the TRAM beyond the texture mapping performed by the interpolator. n Vidia has not shown that the claim language, specification, or prosecution history limits the interpretation of the disputed phrase, leading the court to adopt its ordinary meaning. The phrase "an output coupled to said interpolator for outputting said output rendered pixel" in Claim 1 of the '481 patent is construed to mean that the output is connected to the interpolator for the purpose of outputting the rendered pixel. The court clarifies that the actions of outputting the rendered pixel from the interpolator and from the semiconductor do not need to occur simultaneously. Additionally, an "output rendered pixel" can undergo further on-chip processing beyond texture mapping. For the phrase "outputting said output rendered pixel from said semiconductor chip" in Claim 10, the court finds no requirement for this step to coincide with the outputting from the interpolator. The claim's language does not restrict "output rendered pixel" to a pixel that has only been mapped by the interpolator without further processing. The court thus construes this phrase to imply simply outputting the rendered pixel from the semiconductor chip. Regarding the term "interpolator" in Claims 1 and 10, n Vidia argues for a plain meaning interpretation, whereas Silicon Graphics contends it refers to dedicated circuitry for interpolation. The patent's specification indicates that interpolators produce output texels by interpolating from memory-stored textures and describes the invention as integrating texture memory with interpolation logic for texture mapping. The court finds no support in the patent for Silicon Graphics's interpretation and concludes that "interpolator" should be understood according to its ordinary meaning, which is simply to interpolate, referencing a definition from The American Heritage College Dictionary. The court interprets key terms from the '481 patent as follows: "interpolator" is defined in its ordinary sense as a device that interpolates. The phrase "texture mapping data" in Claims 1 and 10 is understood to refer to complete texture mapping. The term "coupled" in Claim 1 signifies a direct or indirect connection. The phrase "an output coupled to said interpolator for outputting said output rendered pixel" indicates an output connected to the interpolator for producing the rendered pixel. Additionally, "outputting said output rendered pixel from said semiconductor chip" in Claim 10 means producing a rendered pixel from the semiconductor chip. Lastly, "output rendered pixel" in Claims 1 and 10 refers to a pixel that has had texture data and any other data applied to it.